1. Field of the Invention
The present invention relates to a semiconductor tester, and more particularly, to a semiconductor tester which can supply a high-speed clock signal at a low-speed test cycle, as well as to a method of testing a semiconductor using the semiconductor tester.
2. Background Art
FIGS. 7 through 12 show a commonly-employed tester for testing a semiconductor element. FIG. 7 is a schematic representation showing the relationship between a semiconductor element and a semiconductor tester at the time of testing of the semiconductor element. FIG. 8 is a block diagram showing the configuration of a semiconductor tester. FIG. 9 is a schematic representation showing the configuration of a reference-signal-generation circuit. FIG. 10 is a block diagram showing the configuration of a waveform formation circuit. FIGS. 11A through 11C are timing charts representing signal waveforms which arise in the individual sections of the reference-signal-generation circuit. FIGS. 12A and 12B are timing charts representing the signal waveforms which arise in the individual sections of the waveform formation circuit.
In FIG. 7, reference numeral 1 designates a semiconductor element which is an object of measurement (hereinafter referred to as a xe2x80x9csemiconductor element to be measuredxe2x80x9d); 2 designates a semiconductor tester; and 3 designates a device interface board for establishing an interface between the semiconductor tester and the semiconductor element to be measured. As shown in FIG. 8, which illustrates the configuration of the semiconductor tester 2, reference numeral 21 designates a CPU for controlling the entirety of a semiconductor tester; 22 designates a reference-signal-generation circuit for producing a test cycle which serves as a reference-signal of the semiconductor tester; 23 designates a waveform formation circuit for producing a desired waveform from the reference-signal; 24 designates a waveform output circuit for shaping a produced waveform into an output waveform of a set voltage; and 25 designates a power circuit for supplying a supply voltage to the device interface board 3, the semiconductor element 1, and a CPU or for measuring a DC voltage.
As shown in FIG. 9, which illustrates the configuration of the reference-signal-generation circuit 22 of the semiconductor tester, reference numeral 221 designates a reference-clock-signal generation circuit; and 222 designates a counter circuit which counts up a reference clock, produces a test cycle control signal when the resultant count value reaches a predetermined setting, and takes the thus-produced test cycle control signal as a test cycle. A test cycle is determined by means of determining a setting of the counter circuit.
As shown in FIG. 10, which illustrates the configuration of the waveform formation circuit 23, reference numeral 231 designates a timing signal generation circuit for producing leading and trailing edges at predetermined timings on the basis of the test cycle produced by the reference-signal-generation circuit 22; 232 designates a test-pattern storage circuit for storing a test pattern code; and 233 designates a waveform composition circuit for producing the geometry of a waveform on the basis of a timing edge of the timing signal generation circuit and on the basis of a test pattern code stored in a test-pattern storage circuit. The voltage of a waveform having the geometry formed by the waveform composition circuit 233 is set by the waveform output circuit 24, and the waveform is output as a signal.
The operation of a commonly-used semiconductor tester will now be described.
A test cycle is prepared by the reference-signal-generation circuit 22 of the semiconductor tester 2. More specifically, the counter circuit 222 counts up a reference clock signal which is shown in FIG. 11A and is prepared by the reference-clock-signal generation circuit 221 of the reference-signal-generation circuit 22. If, as shown in FIG. 11B, the resultant count value becomes equal to a predetermined setting, a test cycle control signal as shown in FIG. 11C is produced. The thus-produced test cycle control signal is taken as a test cycle. On the basis of the test cycle, the waveform formation circuit 23 produces geometry of an output waveform. More specifically, as shown in FIG. 12A, leading and trailing edges are produced on the basis of the test cycle produced by the reference-signal-generation circuit 22 and at timings set by the timing signal generation circuit 231. On the basis of the leading and trailing edges and a test pattern code stored in the test-pattern storage circuit 232, the waveform composition circuit 233 produces the geometry of a waveform, as shown in FIG. 12B. The waveform output circuit 24 sets the voltage of a waveform having the thus-formed geometry and outputs the waveform as a signal.
At this time, a given test cycle is assigned to all tester pins, and the number of leading and trailing edges of a waveform which can be set within one test cycle is determined for each semiconductor tester. If an attempt is made to produce a clock signal, a clock cycle is limited by the test cycle.
A commonly-used semiconductor tester has a structure as set forth. In a case of testing, through use of the test circuit, of a component of internal circuits (EPROM, ADC, and DAC) of a system LSI and the component operating slower than the operation clock of a CPU, the test cycle to be set in a semiconductor test must be set to the fastest cycle. Such setting is also necessary in a case where a test circuit mounted on a device interface board to be used for a system LSI operates slower than the operation clock of the CPU, and a device is tested through use of the test circuit.
If a test pattern is prepared at this time, the test pattern must be lengthy, because the test pattern is prepared in step with the fastest cycle. Further, storage capacity of a test-pattern storage circuit must become enormous so as to be able to reserve the lengthy test pattern. Although an actual control cycle is of low speed, the operation clock of the CPU is of high speed. Therefore, there is demand for a high-speed semiconductor tester capable of sufficiently producing a control cycle equal to that of the operation clock. If a semiconductor device is tested through use of a high-speed semiconductor tester having a large amount of memory for storing a test pattern, total testing costs become excessive.
The present invention has been conceived to solve such a drawback of the background art and is aimed at providing a low-cost semiconductor tester which saves memory space for storing a test pattern, by means of producing a high-speed clock while preparing a test pattern at a low-speed test cycle and which has a test-pattern storage circuit of small storage capacity, as well as a semiconductor test method using the semiconductor tester.
According to a first aspect of the present invention, there is provided a semiconductor tester comprising: a reference-signal-generation circuit for producing a test cycle to be taken as a reference-signal; a waveform formation circuit for producing the geometry of an output waveform on the basis of the test cycle; and a waveform output circuit which sets the voltage of the geometry of the output waveform and applies the voltage to a semiconductor element to be measured, wherein, in said waveform formation circuit, a ring oscillation circuit having a variable delay circuit is provided and converts the output waveform, which waveform is produced at a predetermined timing, into a high-speed clock waveform.
According to a second aspect of the present invention, there is provided a semiconductor tester comprising: a reference-signal-generation circuit for producing a test cycle to be taken as a reference-signal; a waveform formation circuit for producing the geometry of an output waveform on the basis of the test cycle; and a waveform output circuit which sets the voltage of the geometry of the output waveform and applies the voltage to a semiconductor element to be measured, wherein said reference-signal-generation circuit including: a reference-clock-signal generation circuit for producing a reference clock signal; a counter circuit which counts up the number of reference clock signals and produces a test cycle control signal when the resultant count value reaches a predetermined setting; a setting-value generation circuit for producing a setting value of said counter circuit; and a setting-value control circuit which is connected to said setting-value generation circuit, as required, and multiplies the setting value by an arbitrary value.
According to a third aspect of the present invention, there is provided a semiconductor testing method for use with a semiconductor tester having a reference-signal-generation circuit for producing a test cycle to be taken as a reference-signal, a waveform formation circuit for producing the geometry of an output waveform on the basis of the test cycle, and a waveform output circuit which sets the voltage of the geometry of the output waveform and applies the voltage to a semiconductor element to be measured, the method comprising the steps of: producing a pulse waveform at a programmed timing and on the basis of the test cycle; commencing ring oscillation at a predetermined delay value while the pulse waveform is taken as an input; and outputting a high-speed clock signal to the semiconductor element.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.